The present invention relates generally to logic circuits and more particularly to a logic circuit including a dynamic logic stage driving a dynamic evaluation stage, wherein the dynamic evaluation stage responds to an output signal of the dynamic logic stage for only an initial segment of a first portion of each cycle of a clock wave.
FIG. 1 is a circuit diagram of a dynamic logic circuit previously developed by an employee of the assignee of the present application. The circuit illustrated in the diagram of FIG. 1 has not, to my knowledge, been offered for sale or disclosed on a non-confidential basis to third parties.
The circuit of FIG. 1 includes dynamic logic stage 10, dynamic evaluation stage 12, and inverter, driver stage 14. The circuitry of FIG. 1 is complementary metal oxide semiconductor (CMOS) circuitry on an integrated circuit chip (not shown).
The circuit of FIG. 1 is responsive to binary data input signals IN0, IN1 . . . INn and a clock pulse train (CK) preferably having a high frequency, such as 1 gigahertz (GHz). The clock pulse train has approximately a 50 percent duty cycle so each half cycle of the 1 GHz clock pulse train has a period of approximately 500 picoseconds. First and second opposite DC power supply terminals or rails 18 and 20 are, in a preferred arrangement, respectively at +VDD (+1.3) volts and ground. CMOS dynamic logic stage 10, in the illustrated configuration, includes n N-channel field effect transistors (FETs) 220, 221 . . . 22n, having gate electrodes respectively responsive to binary input signals IN0, IN1 . . . INn and parallel source drain paths connected in shunt between leads 24 and 26. Dynamic logic stage 10 also includes P-channel field effect transistor 28 and N-channel field effect transistor 30, each having a gate electrode responsive to the clock pulse wave train CK. Field effect transistor 28 has its source drain path connected between lead 24 and positive power supply terminal rail 18, while the source drain path of transistor 30 is connected between ground rail 20 and lead 26.
During alternate half cycles of the CK clock pulse wave train, when the clock pulse wave train has a low voltage (CK=0, approximately equal to the. ground potential at rail 20), the clock pulses cause the source drain paths of field effect transistors 28 and 30 to respectively have low and high impedances. The low impedance of field effect transistor 28 connects lead 24 to the positive power supply voltage on terminal or rail 18 and the relatively high source drain impedance of transistor 30 decouples lead 26 from ground rail 20 to enable parasitic capacitance 29 between lead 24 and ground to be precharged. Hence, during the alternate half clock cycles while CK has a low value, capacitance 29 is precharged to a high voltage (i.e., true or binary 1 level).
During the remaining alternate half cycles of the CK clock pulse wave train, while the clock pulse wave train has a high value (approximately equal to the voltage at rail 18), the clock causes the source drain path of field effect transistor 30 to be switched on to provide a low impedance that connects lead 26 to ground simultaneously with the source drain path of field effect transistor 28 being off to provide a high impedance that establishes a load impedance for the voltage developed at lead 24. Evaluation stage 12 detects whether the voltage on parasitic capacitance 29 is high or low while CK=1. Capacitance 29 remains charged to the high voltage while CK=1 only if all of IN0, IN1 . . . INn have low voltages associated with binary 0 values. If any of IN0, IN1 . . . INn has a high voltage, associated with a binary 1 value while CK=1, the source drain paths of transistor 30 and the transistor(s) 220, 221 . . . 22n having gate(s) responsive to a binary 1 signal provide a low impedance path from lead 24 through transistor 30 to discharge capacitance 29 essentially to ground. Based on the foregoing, field effect transistors 220, 221 . . . 22n are connected and function as a NOR logic gate during the clock pulse half cycle while CK=1.
Dynamic evaluation stage 12 responds to the bi-level binary logic signal on capacitance 29 to produce a bi-level output signal designed to have a value complementary to the signal on lead 24 during the clock pulse half cycles while CK=1. CMOS dynamic evaluation stage 12 includes complementary P-channel field effect transistor 36 and N-channel field effect transistor 34 having series connected source drain paths and gate electrodes driven in parallel by the bi-level binary logic signal on capacitance 29. The source drain paths of transistors 34 and 36 are also series connected with the source drain path of N-channel field effect transistor 38, having a gate electrode driven by the CK clock pulse wave train. The source drain paths of field effect transistors 34, 36 and 38 are series connected between power supply rails 18 and 20 so that the sources of field effect transistors 36 and 38 are respectively tied to +VDD rail 18 and ground rail 20.
The drains of transistors 34 and 36 have a common terminal 40, where the bi-level output signal of dynamic evaluation stage 12 is derived. Terminal 40 is tied to the gate of P-channel field effect transistor 42, having a source drain path connected between lead 24 and positive DC power supply rail 18, so that the source drain path of field effect transistor 42 shunts the source drain path of field effect transistor 28.
Field effect transistors 34 and 36 function as an inverter for the bi-level logic signal precharged on parasitic capacitance 29 while CK=1 turns on the source drain path of field effect transistor 38. Consequently, if the voltage on capacitance 29 is high while CK=1, the voltage at terminal 40 is low. The low voltage at terminal 40 forward biases the gate of transistor 42 to turn on the source drain path of transistor 42 which thereby supplies +VDD to capacitance 29 to maintain the voltage on capacitance 29 at the high value. If the voltage on capacitance 29 is precharged low while CK=1, the inverter comprising transistors 34 and 36 supplies a high voltage to terminal 40. The high voltage at terminal 40 back biases the source drain path of transistor 42 so the source drain path of transistor 42 does not couple +VDD at rail 18 to capacitance 29 while CK=1 and the voltage across capacitance 29 remains low.
To assure that the voltage at terminal 40 is high, at +VDD, during the half cycles of the clock pulse wave train while CK=0, the source drain path of P-channel field effect transistor 44 is connected between terminal 40 and the positive power supply voltage +VDD at rail 18 and the gate of field effect transistor 44 is connected to be responsive to the clock pulse wave train. Thereby, during the half cycles of the clock pulse wave train while CK=0, the source drain path of field effect transistor 44 has a low impedance, to tie the voltage at terminal 40 substantially to the +VDD voltage on rail 18.
Inverter 14, which also functions as a driver, responds to the bi-level signal on terminal 40. Inverter 14 has the usual construction, including complementary P-channel field effect transistor 46 and N-channel field effect transistor 48, having series connected source drain paths connected between +VDD power supply rail 18 and ground rail 20. Field effect transistors 46 and 48 have gate electrodes driven in parallel by the bi-level signal at terminal 40 and common drain electrodes at output terminal 50 of the circuit of FIG. 1. During the half cycles of the clock pulse wave train while CK=1, the binary level at terminal 50 is supposed to be the same as the precharged binary level on capacitance 29. During the remaining, alternate half cycles of the clock pulse wave train while CK=0, the voltage at output terminal 50 is essentially at the ground potential of rail 20, by virtue of the source drain path of field effect transistor 48 being turned on by the high voltage at terminal 40.
As illustrated by the waveforms of FIG. 1A during interval T1, each of IN0, IN1 . . . INn is low while CK=1, i.e., during the evaluation half-cycle of the clock. This causes the voltage across capacitor 29 and on lead 24 to be high because of capacitor 29 precharging from +VDD rail 18 through transistor 28 during the previous half-cycle of CK, while CK=0. In response to the high voltage across capacitor 29 and CK=1, transistors 34 and 38 turn on and transistors 36 and 44 turn off causing the voltage on terminal 40 to be low and the voltage on output terminal 50 of inverter 14 to be high. The low voltage at terminal 40 turns on transistor 42 to couple +VDD at rail 18 to capacitor 29 and lead 24 to keep capacitor 29 charged.
In response to a transition of CK from CK=1 to CK=0 at the beginning of interval T2, while all of IN0, IN1 . . . INn=0 (as illustrated in FIG. 1A) transistors 28 and 44 turn on while transistors 30 and 38 turn off. Consequently, +VDD charges capacitor 29 through transistor 28 and supplies a high voltage to terminal 40 via transistor 44. The high voltage across capacitor 29 has no appreciable effect on terminal 40 because CK=0 turns off transistor 38.
If one or more of IN0, IN1 . . . INn (e.g., IN0) goes high while CK=0 during the latter portion of interval T2, as illustrated by the waveforms of FIG. 1A, the voltage across capacitor 29 and on lead 24 stays high because CK=0 turns on transistor 28 and turns off transistor 30, so transistor 28 still couples +VDD at rail 18 to capacitor 29 while transistor 30 provides a high impedance between ground rail 20 and lead 24. Because CK=0 turns off transistor 38 and turns on transistor 44, transistor 44 maintains terminal 40 at +VDD and the high voltage across capacitor 29 has no effect on the voltage at terminal 40 or output terminal 50.
During the next clock half-cycle, when CK=1 as indicated by T3 in FIG. 1A, the voltage across capacitor 29 and on lead 24 drops substantially to ground because of the low impedance path to ground from lead 24 through transistors 220 and 30. The low voltage on lead 24 turns off transistor 34 and has no substantial effect on the high voltage on terminal 40 which is coupled to +VDD through transistor 44. Hence, in the normal operation of FIG. 1, as illustrated in FIG. 1A, the voltage at output terminal 50 during the clock evaluation phase (i.e., CK=1) has a high level only if all of IN0, IN1 . . . Nn=0. The voltage at terminal 50 is always low during the clock precharge phase (i.e., CK=0) and is low during the clock evaluation phase if any of IN0, IN1 . . . Nn=1.
I have discovered that the circuit of FIG. 1 has two problems; viz: (1) the binary values of IN0, IN1 . . . Nn must remain stable during the entire clock pulse wave train half cycle while CK=1 to avoid a glitch in the binary signal at terminal 50 during the clock half cycle while CK=1, and (2) there is a tendency for the binary logic signal on lead 24 to be coupled improperly through dynamic evaluation stage 12.
The glitch occurs if (1) all of IN0, IN1 . . . INn have binary 0 values at the beginning of a first clock cycle while CK=1, and (2) some time toward the end of the first clock cycle while CK=1, one of these values changes from 0 to 1. I have found such a situation is likely to occur because logic signals for the next, (i.e., second) clock cycle while CK=1 are likely to arrive at the gate of one or more of transistors 220, 221 . . . 22n prior to the end of the first half cycle while CK=1. In such a situation, the voltage on lead 24 changes from a high value to a low value some time during the evaluate portion of the first clock cycle while CK=1. The transition from a high to a low voltage on lead 24 during the latter portion of the first clock cycle while CK=1 causes changes in the voltage across capacitance 29 and in the states of the source drain paths of field effect transistors 34, 36 and 42, so that the voltage at terminal 40 changes from a substantially ground level at rail 20, to a high level, equal substantially to the voltage at rail 18. Consequently, the voltage at output terminal 50 of the logic circuit of FIG. 1 changes before the completion of the first clock cycle while CK=1. Circuits responsive to the voltage at terminal 50 thus are likely to respond to the incorrect binary value from the circuit of FIG. 1.
The circuit of FIG. 1 also operates incorrectly and produces a glitch at terminal 50 if any of IN0, IN1 . . . INn, e.g., IN0, has a low to high transition while CK=1. In normal operation if all of IN0, IN1 . . . INn, have low voltages at all times while CK=1, as indicated by interval T1, FIG. 1A, a high voltage is at terminal 50 during CK=1. If there is a low to high voltage transition of any of IN0, IN1 . . . INn while CK=0 and the high voltage persists during CK=1, the voltage at terminal 50 stays low as indicated by T2 and T3. However, if any of IN0, IN1 . . . INn changes from low to high while CK=1, the voltage at terminal 50 goes up in synchronism with the low to high transition and goes down in synchronism with a CK=1 to CK=0 transition.
As illustrated in FIG. 1B, IN0 has a low to high transition during interval T4, between the leading, positive going and trailing, negative going edges of a positive CK half-cycle. The values of IN0=1 and CK=1 respectively cause turn on of transistors 220 and 30 to discharge capacitor 29 and pull down lead 24 substantially to the ground voltage of rail 20. The low voltage on lead 24 turns off transistor 34 and turns on transistor 36 to decouple terminal 40 from ground rail 20 and couple +VDD from rail 18 to terminal 40. Consequently, the voltages at terminal 40 and terminal 50 respectively go up and down until the next CK=1 to CK=0 transition occurs, at which time the voltages at terminal 40 and terminal 50 respectively return to the correct high and low values thereof. The low to high and then high to low transitions during interval T4 are undesirable glitches.
With regard to problem (2), the clock pulse wave train is supplied simultaneously to the gates of each of field effect transistors 28, 30, 38 and 44. Because of leakage factors, transitions on lead 24 are likely to be improperly coupled through dynamic evaluation stage 20 and not drive inverter 14 properly when the integrated circuit is operated at test frequencies that are considerably lower than normal operating frequencies.
FIG. 1C is a series of waveforms for the improper operation of the circuit of FIG. 1 if the value of any of IN0, IN1 . . . INn (e.g., IN0) has a 0 to 1 transition while CK=0 (during interval T5) and then has a 1 to 0 transition while CK=1 (during interval T6). Ideally, under this situation, the voltage at output terminal 50 should remain low during intervals T5 and T6, as discussed previously in connection with intervals T2 and T3 of FIG. 1A. However, in response to the IN0=1 to IN0=0 transition during T6, the voltage at terminal 50 incorrectly changes from a low to a high value, a condition that exists until there is a CK=1 to CK=0 transition. The operation in response to the IN0=0 to IN0=1 transition during T5 and the first part of T6 is the same as in response to the IN0=0 to IN0=1 transition during T2 and T3. However, when the IN0=1 to IN0=0 transition occurs during T6, the low impedance path from ground to lead 24 is no longer present and lead 24 floats. There is a tendency for capacitor 29 to be charged because of the floating condition of lead 24. The charge on capacitor 29 can, under certain circumstances, accumulate to such an extent that the voltage on lead 24 exceeds the threshold, i.e., trigger voltage, for the gate electrode of transistor 34. Such an accumulation of charge is most likely if the frequency of clock is considerably lower than normal, e.g., the clock frequency for the integrated circuit of which the circuit of FIG. 1 is a part is reduced from a normal value of 1 GHz to a frequency of 100 MHz during testing.
In response to the voltage on lead 24 exceeding the trigger voltage of transistor 34 while CK=1 the low impedances of transistors 34 and 38 pull the voltage on terminal 40 down substantially to that of ground rail 20. Consequently, the voltage at output terminal 50 goes high until the next occurrence of a CK=1 to CK=0 transition. The CK=1 to CK=0 transition turns off transistor 38 and turns on transistor 44 to drive terminal 40 and output terminal 50 to high and low voltages, respectively.
It is, accordingly, an object of the present invention to provide a new and improved logic circuit including a dynamic logic stage and a dynamic evaluation stage.
Another object of the present invention is to provide a new and improved CMOS logic circuit including a dynamic logic stage and a dynamic evaluation stage wherein binary signals supplied to the dynamic logic stage do not have to remain stable during a half cycle of a clock pulse wave train while the evaluation stage is enabled.
An additional object of the present invention is to provide a new and improved CMOS logic circuit including a dynamic logic stage and a dynamic evaluation stage wherein glitches in a binary output signal of the logic circuit are avoided even though binary input signals to the logic stage do not remain stable throughout a half cycle of a clock pulse train during which the evaluation stage is enabled.
A further object of the invention is to provide a new and improved logic circuit having a dynamic logic stage and a dynamic evaluation stage, wherein the stages are activated in response to a clock pulse wave train so that a xe2x80x9cracexe2x80x9d does not occur between activation of the evaluation stage and the output of the logic stage.
In accordance with one aspect of the present invention, a logic circuit, including a dynamic logic stage driving a dynamic evaluation stage, is operated by (1) supplying input signals and a clock wave to the dynamic logic stage, (2) deriving from the dynamic logic stage a binary signal that is a logic function of the input signals only during a first portion of each cycle of the clock wave, (3) applying the binary signal and the clock wave to the evaluation stage, and (4) activating the evaluation stage so it is responsive to the binary signal for a period that subsists for only an initial segment of the first portion of each cycle of-the clock wave.
Another aspect of the invention relates to a logic circuit adapted to be responsive to plural binary input signals and a clock wave, wherein the logic circuit comprises (1) a dynamic logic stage connected to be responsive to the binary input signals and the clock wave for deriving a binary logic signal that subsists only during a first portion of each cycle of the clock wave, and (2) a dynamic evaluation stage connected to be responsive to the binary logic signal and the clock. The evaluation stage is arranged to respond to the binary logic signal only during an initial segment of the first portion of each clock cycle.
A further aspect of the invention concerns a CMOS logic circuit adapted to be responsive to plural binary input signals and a clock wave. The CMOS logic circuit comprises first and second DC power supply terminals, a dynamic logic stage and a dynamic evaluation stage. The dynamic logic stage has plural field effect transistors connected to be responsive to the plural binary input signals and the clock wave. The logic stage derives a bi-level logic signal having values determined by (1) the values of the input signals and (2) connections of the plural field effect transistors of the dynamic logic stage. The field effect transistors of the dynamic logic stage have source drain paths connected to the first and second DC power supply terminals and are turned on and off in response to the clock wave. The dynamic logic stage is arranged to derive the bi-level logic signal only during a first portion of each cycle of the clock wave. The first portion of successive cycles of the clock wave alternate with second portions of successive cycles of the clock waves. The bi-level signal has a true value in response to the binary input signals having a predetermined relation.
The dynamic evaluation stage responds to the bi-level logic signal, as well as the clock wave and includes complementary field effect transistors having (a) source drain paths connected in a series circuit to the first and second DC power supply terminals, and (b) gate electrodes responsive to the bi-level logic signal. The evaluation stage has an output terminal in the series circuit. Circuitry responsive to the bi-level logic signal and the clock causes the complementary field effect transistors to be responsive to the bi-level logic signal only during an initial segment of the first portion of each clock cycle.
The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed descriptions of plural specific embodiments thereof, especially when taken in conjunction with the accompanying drawings.